1. Field
This patent specification relates generally to a system and a method for implementing design for testability, and more particularly to such method for identifying the portion with reduced controllability and observability at the stage of hardware function description independent of architecture utilizing test inputs from a pseudorandom number generator in the course of testing large scale integrated devices by means of Logic BIST.
2. Discussion of the Background
An integration of semiconductor devices advances toward higher in density and more complex in operation, the period of time for preparing test patterns for integrated circuits is also increasing to such an extent as to exceed their designing time in some cases.
In the process for fabricating large scale integrated devices, therefore, the method of ‘Design for Testability (DFT)’ has been increasingly indispensable, in that the means for facilitating the generation and execution of device testing is provided in advance at the stage of logic synthesis.
As the DFT method, ‘BIST’ (Built-in Self Test) has been utilized recently, in that a circuit is incorporated into the integrated circuit to automatically execute necessary testing steps, thereby making it feasible to carry out effective testing in the course of, or succeeding to the device formation at production site.
The LSI testing by means of BIST is carried out by providing interiorly a scan path mechanism, feeding test inputs from a pseudorandom number generator to scan input terminals of the scan path mechanism, and then signature analyzing test results output from the mechanism (Japanese Laid-Open Patent Application No. 5-2418882 and Japanese Patent Published No. 2711492).
In the known process flow for design testing by means of ‘LogicBIST’ (Logic Built-in Self Test) incorporated into integrated circuit, there consisted are the steps of first generating by logic synthesis a net list corresponding to the technology from hardware function description independent of architecture, adding thereto a scan path mechanism and LogicBIST controller, and verifying fault detection rates by a fault simulator.
In the case where the fault detection rates are relatively small, the flow instructs to confirm controllability and observability based on the reports from the fault simulator and the net list, subsequently supplement test points, and change the hardware function description independent of architecture, in certain instance.
In the known LogicBIST, however, there gives rise to several drawbacks, which follow.    (1) Since the controllability and observability can be verified only after the fault simulation, a certain time period is required for CAD tool execution with respect to several steps such as logic synthesis, scan path, LogicBIST controller insertion, and fault simulator execution.    (2) Since the analysis of the controllability and observability is verified by the net list at the gate level, the analysis is relatively hard to achieve.    (3) The results obtained by the analysis on the controllability and observability are again relatively hard to be reflected onto the hardware function description independent of architecture.    (4) In the case where test points are inserted to the net list after the analysis on the controllability and observability, timing characteristics of the hardware may degrade.
In contrast, LogicBIST with LFSR (linear Feedback Shift Register) is disclosed in Japanese Laid-Open Patent Applications No. 6-103101 and 8-15382.
The former application '101 discloses methods for analyzing testability on net lists at the gate level to improve fault detection rates. This method, however, does not describe the analysis on the testability at the level of the hardware function description independent of architecture.
The latter application '382 relates to several measures on net lists at the gate level with respect to the prevention from the X state propagation (e.g., from data signatures to become indeterminate and degraded upon the propagation of simulated X values) in LogicBIST, and also to the reduction in the number of times of random number generation. The application, however, does not describe the analysis on the testability at the level of hardware function description independent of architecture.